According the PCI Express base specification when PHY does not meet ZRX-DC specification, after every 100ms timeout the link should transition to recovery state when the link is in low power states. Ports that meet the ZRX-DC specification for 2.5 GT/s while in the L1.Idle state and are therefore not required to implement the 100 ms timeout and transition to Recovery should avoid implementing it, since it will reduce the power savings expected from the L1 state. DesignWare controller provides GEN3_ZRXDC_NONCOMPL field in GEN3_RELATED_OFF to specify about ZRX-DC compliant PHY. Anvesh Salveru (2): dt-bindings: PCI: designware: Add binding for ZRX-DC PHY property PCI: dwc: Add support to handle ZRX-DC Compliant PHYs Documentation/devicetree/bindings/pci/designware-pcie.txt | 2 ++ drivers/pci/controller/dwc/pcie-designware.c | 7 +++++++ drivers/pci/controller/dwc/pcie-designware.h | 3 +++ 3 files changed, 12 insertions(+) -- 2.17.1
