On Thu, 10 Oct 2019 at 02:06, Andrew Jeffery <andrew@xxxxxxxx> wrote: > > RCLK is a fixed 50MHz clock derived from HPLL/HCLK that is described by a > single gate for each MAC. > > Signed-off-by: Andrew Jeffery <andrew@xxxxxxxx> Reviewed-by: Joel Stanley <joel@xxxxxxxxx>
