On Thu, Jul 4, 2019 at 7:23 AM Martin Blumenstingl <martin.blumenstingl@xxxxxxxxxxxxxx> wrote: > > Add the bindings for the PCIe PHY on Lantiq VRX200 and ARX300 SoCs. > The IP block contains settings for the PHY and a PLL. > The PLL mode is configurable through a dedicated #phy-cell in .dts. > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@xxxxxxxxxxxxxx> > --- > .../bindings/phy/lantiq,vrx200-pcie-phy.yaml | 95 +++++++++++++++++++ > .../dt-bindings/phy/phy-lantiq-vrx200-pcie.h | 11 +++ > 2 files changed, 106 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml > create mode 100644 include/dt-bindings/phy/phy-lantiq-vrx200-pcie.h > > diff --git a/Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml > new file mode 100644 > index 000000000000..8a56a8526cef > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml > @@ -0,0 +1,95 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Lantiq VRX200 and ARX300 PCIe PHY Device Tree Bindings > + > +maintainers: > + - Martin Blumenstingl <martin.blumenstingl@xxxxxxxxxxxxxx> > + > +properties: > + "#phy-cells": > + const: 1 > + description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h> > + > + compatible: > + enum: > + - lantiq,vrx200-pcie-phy > + - lantiq,arx300-pcie-phy > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: PHY module clock > + - description: PDI register clock > + > + clock-names: > + items: > + - const: phy > + - const: pdi > + > + resets: > + items: > + - description: exclusive PHY reset line > + - description: shared reset line between the PCIe PHY and PCIe controller > + > + resets-names: This breaks 'make dt_binding_check'. It should be 'reset-names'. Rob
