Add sound node and the clock configurations for the I2S controller
for audio support on the Exynos5250 SoC Arndale boards with
WM1811 based audio daughter board.
We need to increase drive strength of the I2S bus, otherwise
the audio CODEC doesn't work. Likely the CODEC's master clock
is the main issue here.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@xxxxxxxxxxx>
---
Changes since v1:
- moved &clock, &clock_audss parts to preserve alphabetical order
---
arch/arm/boot/dts/exynos5250-arndale.dts | 27 +++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index dc6fa6fe83f1..7247efe2ec12 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -11,6 +11,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/clock/samsung,s2mps11.h>
+#include <dt-bindings/sound/samsung-i2s.h>
#include "exynos5250.dtsi"
/ {
@@ -135,6 +136,12 @@
};
};
+ sound {
+ compatible = "samsung,arndale-wm1811";
+ samsung,audio-cpu = <&i2s0>;
+ samsung,audio-codec = <&wm1811>;
+ };
+
fixed-rate-clocks {
xxti {
compatible = "samsung,clock-xxti";
@@ -151,6 +158,16 @@
};
};
+&clock {
+ assigned-clocks = <&clock CLK_FOUT_EPLL>;
+ assigned-clock-rates = <49152000>;
+};
+
+&clock_audss {
+ assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>;
+ assigned-clock-parents = <&clock CLK_FOUT_EPLL>;
+};
+
&cpu0 {
cpu0-supply = <&buck2_reg>;
};
@@ -502,9 +519,11 @@
&i2c_3 {
status = "okay";
- wm1811a@1a {
+ wm1811: codec@1a {
compatible = "wlf,wm1811";
reg = <0x1a>;
+ clocks = <&i2s0 CLK_I2S_CDCLK>;
+ clock-names = "MCLK1";
AVDD2-supply = <&main_dc_reg>;
CPVDD-supply = <&main_dc_reg>;
@@ -540,9 +559,15 @@
};
&i2s0 {
+ assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;
+ assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>;
status = "okay";
};
+&i2s0_bus {
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
+};
+
&mixer {
status = "okay";
};
--
2.17.1
