Hi Jerome, On 2019/9/9 19:36, Jerome Brunet wrote: > > On Sat 07 Sep 2019 at 17:02, Martin Blumenstingl wrote: > >> Hi Jianxin, >> >> On Fri, Sep 6, 2019 at 7:58 AM Jianxin Pan <jianxin.pan@xxxxxxxxxxx> wrote: >> [...] >>>> also I'm a bit surprised to see no busses (like aobus, cbus, periphs, ...) here >>>> aren't there any busses defined in the A1 SoC implementation or are >>>> were you planning to add them later? >>> Unlike previous series,there is no Cortex-M3 AO CPU in A1, and there is no AO/EE power domain. >>> Most of the registers are on the apb_32b bus. aobus, cbus and periphs are not used in A1. >> OK, thank you for the explanation >> since you're going to re-send the patch anyways: can you please >> include the apb_32b bus? > > unless there is an 64 bits apb bus as well, I suppose 'apb' would be enough ? > There is no 64bits apb bus in A1, only apb32. Unlike the previous series, For A1 and C1, we can not get bus information for each register from the memmap and datesheet. Do we need to add bus description for them too? If yes, I can add 'apb' . >> all other upstream Amlogic .dts are using the bus definitions, so that >> will make A1 consistent with the other SoCs >> >> >> Martin > > . >
