On Wed, Jul 31, 2019 at 02:21:21PM +0200, Miquel Raynal wrote: > Armada CP110 PCIe controller can have from one to four PHYs for > configuring SERDES lanes (PCIe x1, PCIe x2 or PCIe x4). Describe the > phys and phy-names properties in the bindings. > > Signed-off-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx> > --- > Documentation/devicetree/bindings/pci/pci-armada8k.txt | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt > index 9e3fc15e1af8..7cf12162aa4e 100644 > --- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt > +++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt > @@ -17,6 +17,12 @@ Required properties: > name must be "core" for the first clock and "reg" for the second > one > > +Optional properties: > +- phys: phandle(s) to PHY node(s) following the generic PHY bindings. > + Either 1, 2 or 4 PHYs might be needed depending on the number of > + PCIe lanes. > +- phy-names: names of the PHYs. You need to enumerate what the names are. Based on your example in v2, I don't think the names are really valuable unless you can skip lanes. Rob
