Gentle ping... > From: Anson Huang <Anson.Huang@xxxxxxx> > > The system counter block guide states that the base clock is internally divided > by 3 before use, that means the clock input of system counter defined in DT > should be base clock which is normally from OSC, and then internally divided > by 3 before use. > > Signed-off-by: Anson Huang <Anson.Huang@xxxxxxx> > --- > Changes since V4: > - to solve the clock driver probed after system counter driver issue, > now we can easily switch to > use fixed clock defined in DT and get its rate, then divided by 3 to > get real clock rate for > system counter driver, no need to add "clock-frequency" property in > DT. > --- > drivers/clocksource/timer-imx-sysctr.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/clocksource/timer-imx-sysctr.c > b/drivers/clocksource/timer-imx-sysctr.c > index fd7d680..b7c80a3 100644 > --- a/drivers/clocksource/timer-imx-sysctr.c > +++ b/drivers/clocksource/timer-imx-sysctr.c > @@ -20,6 +20,8 @@ > #define SYS_CTR_EN 0x1 > #define SYS_CTR_IRQ_MASK 0x2 > > +#define SYS_CTR_CLK_DIV 0x3 > + > static void __iomem *sys_ctr_base; > static u32 cmpcr; > > @@ -134,6 +136,9 @@ static int __init sysctr_timer_init(struct device_node > *np) > if (ret) > return ret; > > + /* system counter clock is divided by 3 internally */ > + to_sysctr.of_clk.rate /= SYS_CTR_CLK_DIV; > + > sys_ctr_base = timer_of_base(&to_sysctr); > cmpcr = readl(sys_ctr_base + CMPCR); > cmpcr &= ~SYS_CTR_EN; > -- > 2.7.4
