On Sat, Jul 27, 2019 at 10:28 PM Jernej Škrabec <jernej.skrabec@xxxxxxxx> wrote: > > Dne sobota, 27. julij 2019 ob 12:50:08 CEST je Maxime Ripard napisal(a): > > On Fri, Jul 26, 2019 at 08:40:44PM +0200, Jernej Skrabec wrote: > > > PWM core has an option to bypass whole logic and output unchanged source > > > clock as PWM output. This is achieved by enabling bypass bit. > > > > > > Note that when bypass is enabled, no other setting has any meaning, not > > > even enable bit. > > > > > > This mode of operation is needed to achieve high enough frequency to > > > serve as clock source for AC200 chip, which is integrated into same > > > package as H6 SoC. > > > > > > Signed-off-by: Jernej Skrabec <jernej.skrabec@xxxxxxxx> > > > > It doesn't seem to be available on the A10 (at least) though. The A13 > > seem to have it, so you should probably check that, and make that > > conditional to the compatible if not available on all of them. > > Ok, can you suggest the name for the quirk? "has_bypass" is suspiciously > similar to "has_prescaler_bypass". has_direct_mod_clk_output? > Also, how to name these sun4i_pwm_data structures? Now that there are (will > be) three new quirks, name of the structure would be just too long, like > "sun50i_pwm_dual_prescaler_bypass_clk_rst_bypass". Just use the SoC model. Any later ones that have the same quirks will likely use the same compatible string anyway. ChenYu
