Allwinner H6 SoC has PWM core which is basically the same as that found in A20, it's just depends on additional bus clock and reset line. This series adds support for it and extends PWM driver functionality in a way that it's now possible to bypass whole core and output PWM source clock directly as a PWM signal. This functionality is needed by AC200 chip, which is bundled in same physical package as H6 SoC, to serve as a clock source of 24 MHz. AC200 clock input pin is bonded internally to the second PWM channel. I would be grateful if anyone can test this patch series for any kind of regression on other SoCs. Please take a look. Best regards, Jernej Jernej Skrabec (6): dt-bindings: pwm: allwinner: Add H6 PWM description pwm: sun4i: Add a quirk for reset line pwm: sun4i: Add a quirk for bus clock pwm: sun4i: Add support for H6 PWM pwm: sun4i: Add support to output source clock directly arm64: dts: allwinner: h6: Add PWM node .../bindings/pwm/allwinner,sun4i-a10-pwm.yaml | 36 +++++++- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 +++ drivers/pwm/pwm-sun4i.c | 83 ++++++++++++++++++- 3 files changed, 125 insertions(+), 4 deletions(-) -- 2.22.0
