Add adma lpcg clocks
Cc: Rob Herring <robh+dt@xxxxxxxxxx>
Cc: Mark Rutland <mark.rutland@xxxxxxx>
Cc: devicetree@xxxxxxxxxxxxxxx
Cc: Shawn Guo <shawnguo@xxxxxxxxxx>
Cc: Sascha Hauer <kernel@xxxxxxxxxxxxxx>
Cc: Fabio Estevam <fabio.estevam@xxxxxxx>
Signed-off-by: Dong Aisheng <aisheng.dong@xxxxxxx>
---
ChangeLog:
v1->v2:
* Use old SCU clock binding temporarily to avoid build warning due to SCU
clock cell will be changed to 2.
* add power domain property
---
arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi | 98 +++++++++++++++++++++++++
1 file changed, 98 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
index 8738028..f0681a7 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
@@ -4,12 +4,22 @@
* Dong Aisheng <aisheng.dong@xxxxxxx>
*/
+#include <dt-bindings/firmware/imx/rsrc.h>
+
adma_subsys: bus@59000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x59000000 0x0 0x59000000 0x2000000>;
+ dma_ipg_clk: clock-dma-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <120000000>;
+ clock-output-names = "dma_ipg_clk";
+ };
+
+ /* LPCG clocks */
adma_lpcg: clock-controller@59000000 {
reg = <0x59000000 0x2000000>;
#clock-cells = <1>;
@@ -55,6 +65,50 @@ adma_subsys: bus@59000000 {
status = "disabled";
};
+ uart0_lpcg: clock-controller@5a460000 {
+ reg = <0x5a460000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_ADMA_UART0_CLK>,
+ <&dma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "uart0_lpcg_baud_clk",
+ "uart0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_UART_0>;
+ };
+
+ uart1_lpcg: clock-controller@5a470000 {
+ reg = <0x5a470000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_ADMA_UART1_CLK>,
+ <&dma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "uart1_lpcg_baud_clk",
+ "uart1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_UART_1>;
+ };
+
+ uart2_lpcg: clock-controller@5a480000 {
+ reg = <0x5a480000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_ADMA_UART2_CLK>,
+ <&dma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "uart2_lpcg_baud_clk",
+ "uart2_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_UART_2>;
+ };
+
+ uart3_lpcg: clock-controller@5a490000 {
+ reg = <0x5a490000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_ADMA_UART3_CLK>,
+ <&dma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "uart3_lpcg_baud_clk",
+ "uart3_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_UART_3>;
+ };
+
adma_i2c0: i2c@5a800000 {
reg = <0x5a800000 0x4000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
@@ -102,4 +156,48 @@ adma_subsys: bus@59000000 {
power-domains = <&pd IMX_SC_R_I2C_3>;
status = "disabled";
};
+
+ i2c0_lpcg: clock-controller@5ac00000 {
+ reg = <0x5ac00000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_ADMA_I2C0_CLK>,
+ <&dma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "i2c0_lpcg_clk",
+ "i2c0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_I2C_0>;
+ };
+
+ i2c1_lpcg: clock-controller@5ac10000 {
+ reg = <0x5ac10000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_ADMA_I2C1_CLK>,
+ <&dma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "i2c1_lpcg_clk",
+ "i2c1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_I2C_1>;
+ };
+
+ i2c2_lpcg: clock-controller@5ac20000 {
+ reg = <0x5ac20000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_ADMA_I2C2_CLK>,
+ <&dma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "i2c2_lpcg_clk",
+ "i2c2_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_I2C_2>;
+ };
+
+ i2c3_lpcg: clock-controller@5ac30000 {
+ reg = <0x5ac30000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_ADMA_I2C3_CLK>,
+ <&dma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "i2c3_lpcg_clk",
+ "i2c3_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_I2C_3>;
+ };
};
--
2.7.4
