The FSYS APB bus OPP table has been aligned to the new parent rate. This
patch sets the proper parent and picks the init frequency before the
devfreq governor starts working. It sets also parent rate (MPLL to
600MHz).
Signed-off-by: Lukasz Luba <l.luba@xxxxxxxxxxxxxxxxxxx>
---
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 0e71ba64a4fe..6225d044d01c 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -67,6 +67,11 @@
&bus_fsys_apb {
devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_MOUT_PCLK200_FSYS>,
+ <&clock CLK_DOUT_PCLK200_FSYS>,
+ <&clock CLK_FOUT_MPLL>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_MPLL>;
+ assigned-clock-rates = <0>, <200000000>,<600000000>;
status = "okay";
};
--
2.17.1
