The bus_gen OPP table has been aligned to the new parent rate. This patch
sets the proper parent and picks the init frequency before the devfreq
governor starts working. It sets also parent rate (MPLL to 600MHz).
Signed-off-by: Lukasz Luba <l.luba@xxxxxxxxxxxxxxxxxxx>
---
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 6225d044d01c..75664ff6d966 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -102,6 +102,10 @@
&bus_gen {
devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_MOUT_ACLK266>,
+ <&clock CLK_DOUT_ACLK266>, <&clock CLK_FOUT_MPLL>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_MPLL>;
+ assigned-clock-rates = <0>, <300000000>,<600000000>;
status = "okay";
};
--
2.17.1
