On Exynos5422 there is a dedicated clock hierarchy for ACLK_266_ISP which
should be set to proper values to fully use the HW performance.
The old settings left after boot set minimal values to this bus.
In the Exynos5420 the bus is connected to ACLK_266 so there is no need for
aligning the values. In the Exynos5422 the proper hierarchy of these
clocks should be model in the software to use the full HW feature set.
The patch sets proper parent (MPLL) and initial frequency to the bus also
enabling it.
Signed-off-by: Lukasz Luba <l.luba@xxxxxxxxxxxxxxxxxxx>
---
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index d278339f259c..c770d17141e8 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -187,6 +187,17 @@
status = "okay";
};
+&bus_isp266 {
+ devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_MOUT_ACLK266_ISP>,
+ <&clock CLK_MOUT_USER_ACLK266_ISP>,
+ <&clock CLK_DOUT_ACLK266_ISP>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_MPLL>,
+ <&clock CLK_MOUT_SW_ACLK266_ISP>;
+ assigned-clock-rates = <0>, <0>,<300000000>;
+ status = "okay";
+};
+
&cpu0 {
cpu-supply = <&buck6_reg>;
};
--
2.17.1
