The bus_disp1 OPP table has been aligned to the new parent rate. This patch
sets the proper frequencies before the devfreq governor starts working. It
sets 200MHz to bus ACLK_200_DISP1 which is controlled via CLK_DOUT_ACLK200
and 400MHz to ACLK400_DISP1 which is controlled via CLK_DOUT_ACLK400_DISP1.
Signed-off-by: Lukasz Luba <l.luba@xxxxxxxxxxxxxxxxxxx>
---
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 2cfe1effe290..fac5659516ad 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -150,6 +150,9 @@
&bus_disp1 {
devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_DOUT_ACLK200>,
+ <&clock CLK_DOUT_ACLK400_DISP1>;
+ assigned-clock-rates = <200000000>, <400000000>;
status = "okay";
};
--
2.17.1
