On 19-07-15 12:43:05, Guido Günther wrote:
> Add a node for the Mixel MIPI D-PHY, "disabled" by default.
>
> Signed-off-by: Guido Günther <agx@xxxxxxxxxxx>
> Acked-by: Angus Ainslie (Purism) <angus@xxxxxxxx>
> ---
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index d09b808eff87..891ee7578c2d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -728,6 +728,19 @@
> status = "disabled";
> };
>
> + dphy: dphy@30a00300 {
> + compatible = "fsl,imx8mq-mipi-dphy";
> + reg = <0x30a00300 0x100>;
> + clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
> + clock-names = "phy_ref";
> + assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
> + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
> + assigned-clock-rates = <24000000>;
We have the following in the clk-imx8mq in the vendor tree:
clk_set_parent(clks[IMX8MQ_VIDEO_PLL1_BYPASS], clks[IMX8MQ_VIDEO_PLL1]);
This unbypasses the video pll 1. And then we also have this:
/* config video_pll1 clock */
clk_set_parent(clks[IMX8MQ_VIDEO_PLL1_REF_SEL], clks[IMX8MQ_CLK_27M]);
clk_set_rate(clks[IMX8MQ_VIDEO_PLL1], 593999999);
But none of that is acceptable upstream since the clock provider should not
use clock consumer API.
So please update the assigned-clock* properties to something like this:
assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
<&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
<&clk IMX8MQ_CLK_DSI_PHY_REF>,
<&clk IMX8MQ_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MQ_CLK_27M>,
<&clk IMX8MQ_VIDEO_PLL1>,
<&clk IMX8MQ_VIDEO_PLL1_OUT>
<0>;
assigned-clock-rates = <0>,
<0>,
<24000000>,
<593999999>;
I've written this without testing, so please do test it on your setup.
> + #phy-cells = <0>;
> + power-domains = <&pgc_mipi>;
> + status = "disabled";
> + };
> +
> i2c1: i2c@30a20000 {
> compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
> reg = <0x30a20000 0x10000>;
> --
> 2.20.1
>
