Add support to configure cache type for 4 different transfer types: Data Read,
Desc Read, Data Write and Desc write. For each treasfer type, controller has a
4-bit register field to enable different cache type.
Some Layerscape platforms might need this to resolve USB detect problem
when DWC3 node apply dma-coherent.
Signed-off-by: Ran Wang <ran.wang_1@xxxxxxx>
---
Change in v2:
- Change most program logic to meet new DTS property define.
- Rename related register address macros.
- Rename function dwc3_enable_snooping() to dwc3_set_cache_type().
drivers/usb/dwc3/core.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++++
drivers/usb/dwc3/core.h | 12 ++++++++++
2 files changed, 76 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 4aff1d8..43bdd73 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -284,6 +284,69 @@ static const struct clk_bulk_data dwc3_core_clks[] = {
};
/*
+ * dwc3_set_cache_type - Configure cache type
+ * @dwc3: Pointer to our controller context structure
+ */
+static void dwc3_set_cache_type(struct dwc3 *dwc)
+{
+ int ret;
+ u32 tmp, reg, cache_type;
+ struct fwnode_handle *fwnode;
+
+ reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
+ tmp = reg;
+
+ fwnode = device_get_named_child_node(dwc->dev, "cache_type");
+ if (!fwnode) {
+ dev_info(dwc->dev, "Cache_type node no found, skip.\n");
+ return;
+ }
+
+ ret = fwnode_property_read_u32(fwnode,
+ "transfer_type_datard", &cache_type);
+ if (ret) {
+ dev_err(dwc->dev,
+ "Can't find property transfer_type_datard.\n");
+ return;
+ }
+ reg &= ~DWC3_GSBUSCFG0_DATARD(~0);
+ reg |= DWC3_GSBUSCFG0_DATARD(cache_type);
+
+ ret = fwnode_property_read_u32(fwnode,
+ "transfer_type_descrd", &cache_type);
+ if (ret) {
+ dev_err(dwc->dev,
+ "Can't find property transfer_type_descrd.\n");
+ return;
+ }
+ reg &= ~DWC3_GSBUSCFG0_DESCRD(~0);
+ reg |= DWC3_GSBUSCFG0_DESCRD(cache_type);
+
+ ret = fwnode_property_read_u32(fwnode,
+ "transfer_type_datawr", &cache_type);
+ if (ret) {
+ dev_err(dwc->dev,
+ "Can't find property transfer_type_datawr.\n");
+ return;
+ }
+ reg &= ~DWC3_GSBUSCFG0_DATAWR(~0);
+ reg |= DWC3_GSBUSCFG0_DATAWR(cache_type);
+
+ ret = fwnode_property_read_u32(fwnode,
+ "transfer_type_descwr", &cache_type);
+ if (ret) {
+ dev_err(dwc->dev,
+ "Can't find property transfer_type_descwr.\n");
+ return;
+ }
+ reg &= ~DWC3_GSBUSCFG0_DESCWR(~0);
+ reg |= DWC3_GSBUSCFG0_DESCWR(cache_type);
+
+ if (tmp != reg)
+ dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
+}
+
+/*
* dwc3_frame_length_adjustment - Adjusts frame length if required
* @dwc3: Pointer to our controller context structure
*/
@@ -942,6 +1005,7 @@ static int dwc3_core_init(struct dwc3 *dwc)
dwc3_frame_length_adjustment(dwc);
dwc3_set_incr_burst_type(dwc);
+ dwc3_set_cache_type(dwc);
usb_phy_set_suspend(dwc->usb2_phy, 0);
usb_phy_set_suspend(dwc->usb3_phy, 0);
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index f19cbeb..24a613f 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -165,6 +165,18 @@
/* Bit fields */
/* Global SoC Bus Configuration INCRx Register 0 */
+#define DWC3_GSBUSCFG0_DATARD_SHIFT 28
+#define DWC3_GSBUSCFG0_DATARD(n) (((n) & 0xf) \
+ << DWC3_GSBUSCFG0_DATARD_SHIFT)
+#define DWC3_GSBUSCFG0_DESCRD_SHIFT 24
+#define DWC3_GSBUSCFG0_DESCRD(n) (((n) & 0xf) \
+ << DWC3_GSBUSCFG0_DESCRD_SHIFT)
+#define DWC3_GSBUSCFG0_DATAWR_SHIFT 20
+#define DWC3_GSBUSCFG0_DATAWR(n) (((n) & 0xf) \
+ << DWC3_GSBUSCFG0_DATAWR_SHIFT)
+#define DWC3_GSBUSCFG0_DESCWR_SHIFT 16
+#define DWC3_GSBUSCFG0_DESCWR(n) (((n) & 0xf) \
+ << DWC3_GSBUSCFG0_DESCWR_SHIFT)
#define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */
#define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */
#define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */
--
2.7.4
