Hi Rob, > -----Original Message----- > From: openbmc > [mailto:openbmc-bounces+george.hung=quantatw.com@xxxxxxxxxxxxxxxx] On > Behalf Of Rob Herring > Sent: Tuesday, July 09, 2019 9:41 AM > To: George Hung > Cc: Mark Rutland; Linus Walleij; Tali Perry; paulmck@xxxxxxxxxxxxx; > wak@xxxxxxxxxx; benjaminfair@xxxxxxxxxx; openbmc@xxxxxxxxxxxxxxxx; > tomer.maimon@xxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; Borislav Petkov; > Avi.Fishman@xxxxxxxxxxx; Jonathan Cameron; Mauro Carvalho Chehab; > linux-edac; Patrick Venture; Nicolas Ferre; linux-kernel; James Morse; Greg > Kroah-Hartman; davem@xxxxxxxxxxxxx > Subject: Re: [PATCH 5.2 v2 2/2] dt-binding: edac: add NPCM ECC > documentation > > On Wed, Jun 05, 2019 at 10:12:53PM +0800, George Hung wrote: > > Add device tree documentation for Nuvoton BMC ECC > > > > Signed-off-by: George Hung <ghung.quanta@xxxxxxxxx> > > --- > > .../bindings/edac/npcm7xx-sdram-edac.txt | 17 > +++++++++++++++++ > > 1 file changed, 17 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/edac/npcm7xx-sdram-edac.txt > > > > diff --git > > a/Documentation/devicetree/bindings/edac/npcm7xx-sdram-edac.txt > > b/Documentation/devicetree/bindings/edac/npcm7xx-sdram-edac.txt > > new file mode 100644 > > index 000000000000..dd4dac59a5bd > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/edac/npcm7xx-sdram-edac.txt > > @@ -0,0 +1,17 @@ > > +Nuvoton NPCM7xx SoC EDAC device driver > > + > > +The Nuvoton NPCM7xx SoC supports DDR4 memory with/without ECC and > the > > +driver uses the EDAC framework to implement the ECC detection and > corrtection. > > + > > +Required properties: > > +- compatible: should be "nuvoton,npcm7xx-sdram-edac" > > Is this for the whole SDRAM controller or just ECC related registers? > In the former case, the naming should just reflect the block name and not a > Linux term. Sorry for confused naming, the address space is for the whole memory controller registers indeed, but the driver only uses the ECC related registers. Should I change the name to "nuvoton,npcm7xx-edac" ? > > > +- reg: Memory controller register set should be <0xf0824000 > 0x1000> > > +- interrupts: should be MC interrupt #25 > > + > > +Example: > > + > > + mc: memory-controller@f0824000 { > > + compatible = "nuvoton,npcm7xx-sdram-edac"; > > + reg = <0xf0824000 0x1000>; > > + interrupts = <0 25 4>; > > + }; > > -- > > 2.21.0 > >
