Hi Miquel,
>
> > > > > > > > +static void mxic_nand_select_chip(struct nand_chip *chip,
int
> >
> > > > chipnr)
> > > > > > >
> > > > > > > _select_target() is preferred now
> > > > > >
> > > > > > Do you mean I implement mxic_nand_select_target() to control
#CS ?
> > > > > >
> > > > > > If so, I need to call mxic_nand_select_target( ) to control
#CS ON
> > > > > > and then #CS OFF in _exec_op() due to nand_select_target()<in
> > > > nand_base,c>
> > > > > > is still calling chip->legacy.select_chip ?
> > > > >
> > > > > You must forget about the ->select_chip() callback. Now it
should be
> > > > > handled directly from the controller driver. Please have a look
at
> > the
> > > > > commit pointed against the marvell_nand.c driver.
> > > >
> > > > I have no Marvell NFC datasheet and have one question.
> > > >
> > > > In marvell_nand.c, there is no xxx_deselect_target() or
> > > > something like that doing #CS OFF.
> > > > marvell_nfc_select_target() seems always to make one of chip or
die
> > > > #CS keep low.
> > > >
> > > > Is it right ?
> > >
> > > Yes, AFAIR there is no "de-assert" mechanism in this controller.
> > >
> > > >
> > > > How to make all #CS keep high for NAND to enter
> > > > low-power standby mode if driver don't use "legacy.select_chip()"
?
> > >
> > > See commit 02b4a52604a4 ("mtd: rawnand: Make ->select_chip()
optional
> > > when ->exec_op() is implemented") which states:
> > >
> > > "When [->select_chip() is] not implemented, the core is
assuming
> > > the CS line is automatically asserted/deasserted by the driver
> > > ->exec_op() implementation."
> > >
> > > Of course, the above is right only when the controller driver
supports
> > > the ->exec_op() interface.
> >
> > Currently, it seems that we will get the incorrect data and error
> > operation due to CS in error toggling if CS line is controlled in
> > ->exec_op().
>
> Most of the chips today are CS-don't-care, which chip are you using?
I think CS-don't-care means read-write operation for NAND device to reside
on the same memory bus as other Flash or SRAM devices. Other devices on
the
memory bus can then be accessed while the NAND Flash is busy with internal
operations. This capability is very important for designs that require
multiple
NAND Flash devices on the same bus.
>
> Is this behavior publicly documented?
>
CS# pin goes High enter standby mode to reduce power consumption,
i.e,. standby mode w/ CS# keep High, standby current: 10 uA (Typ for 3.3V
NAND)
otherwise, current is more than 1 mA.
i.e,. page read current, 25 mA (Typ for 3.3V NAND)
> Is this LPM mode always activated?
>
> > i.e,.
> >
> > 1) In nand_onfi_detect() to call nand_exec_op() twice by
> > nand_read_param_page_op() and annd_read_data_op()
> >
> > 2) In nand_write_page_xxx to call nand_exec_op() many times by
> > nand_prog_page_begin_op(), nand_write_data_op() and
> > nand_prog_page_end_op().
> >
> >
> > Should we consider to add a CS line controller in struct
nand_controller
> > i.e,.
> >
> > struct nand_controller {
> > struct mutex lock;
> > const struct nand_controller_ops *ops;
> > + void (*select_chip)(struct nand_chip *chip, int cs);
> > };
> >
> > to replace legacy.select_chip() ?
> >
>
> No, if really needed, we could add a "macro op done" flag in the nand
> operation structure.
>
Is this "macron op done" flag good for multiple NAND devices on
the same bus ?
Any other way to control CS# pin? if user application is really
care of power consumption, i.e,. loT.
>
> Thanks,
> Miquèl
thanks & best regards,
Mason
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