From: <itdaniher@xxxxxxxxx> Following the discussion here: https://github.com/rockchip-linux/kernel/issues/123 it can be seen that these are the changes needed to enable the use of the hardware watchdog in the rk3328 SoC. This is in line with past changes for the rk3288: http://lists.infradead.org/pipermail/linux-rockchip/2015-January/002314.html Signed-off-by: Leonidas P. Papadakos <papadakospan@xxxxxxxxx> --- drivers/clk/rockchip/clk-rk3328.c | 9 +++++++++ include/dt-bindings/clock/rk3328-cru.h | 1 + 2 files changed, 10 insertions(+) diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c index 076b9777a..546ee0ab7 100644 --- a/drivers/clk/rockchip/clk-rk3328.c +++ b/drivers/clk/rockchip/clk-rk3328.c @@ -876,6 +876,8 @@ static const char *const rk3328_critical_clocks[] __initconst = { static void __init rk3328_clk_init(struct device_node *np) { + struct clk *clk; + struct rockchip_clk_provider *ctx; void __iomem *reg_base; @@ -892,6 +894,13 @@ static void __init rk3328_clk_init(struct device_node *np) return; } + clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_bus", 0, 1, 1); + if (IS_ERR(clk)) + pr_warn("%s: could not register clock pclk_wdt: %ld\n", + __func__, PTR_ERR(clk)); + else + rockchip_clk_add_lookup(ctx, clk, PCLK_WDT); + rockchip_clk_register_plls(ctx, rk3328_pll_clks, ARRAY_SIZE(rk3328_pll_clks), RK3328_GRF_SOC_STATUS0); diff --git a/include/dt-bindings/clock/rk3328-cru.h b/include/dt-bindings/clock/rk3328-cru.h index afb811340..555b4ff66 100644 --- a/include/dt-bindings/clock/rk3328-cru.h +++ b/include/dt-bindings/clock/rk3328-cru.h @@ -164,6 +164,7 @@ #define PCLK_DCF 233 #define PCLK_SARADC 234 #define PCLK_ACODECPHY 235 +#define PCLK_WDT 236 /* hclk gates */ #define HCLK_PERI 308 -- 2.21.0
