Hi Mark,
On Fri, Apr 11, 2014 at 4:18 AM, Mark Brown <broonie@xxxxxxxxxx> wrote:
> On Thu, Apr 10, 2014 at 05:43:49PM +0530, Harini Katakam wrote:
>> Add driver for Cadence SPI controller. This is used in Xilinx Zynq.
>
> This looks mostly good, the issues below are very small.
>
>> +static int __maybe_unused cdns_spi_suspend(struct device *dev)
>> +{
>> + struct platform_device *pdev = container_of(dev,
>> + struct platform_device, dev);
>> + struct spi_master *master = platform_get_drvdata(pdev);
>> + struct cdns_spi *xspi = spi_master_get_devdata(master);
>> +
>> + spi_master_suspend(master);
>> +
>> + clk_disable(xspi->ref_clk);
>> +
>> + clk_disable(xspi->pclk);
>
> You're only doing clk_disable() here, I would expect the clocks to also
> be unprepared over suspend - there is no value in leaving them prepared
> that I can see. Just use clk_unprepare_disable().
>
> It would also be good (though not essential) to implement runtime PM and
> disable the clocks while there are no transfers in progress for a small
> power saving. The auto_runtime_pm feature in the core will do the
> runtime PM calls for you.
>
> Otherwise this looks good.
Thanks. I'll make these changes and send a v4 next week.
Regards,
Harini
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