On 5/31/2019 4:15 AM, Herrenschmidt, Benjamin wrote:
On Thu, 2019-05-30 at 11:19 -0700, Boris Petkov wrote:
On May 30, 2019 3:15:29 AM PDT, Hanna Hawa <hhhawa@xxxxxxxxxx> wrote:
Add support for error detection and correction for Amazon's
Annapurna
Labs SoCs for L1/L2 caches.
So this should be a driver for the whole annapurna platform and not
only about the RAS functionality in an IP like the caches. See other
ARM EDAC drivers in drivers/edac/ for an example.
This isn't terribly helpful, there's nothing telling anybody which of
those files corresponds to an ARM SoC :-)
That said ...
You really want a single EDAC driver that contains all the stuff for
the caches, the memory controller, etc... ?
The idea here was to separate the core L1/L2 EDAC from the memory
controller EDAC I think ... Roben, Hanna, can you describe the long run
strategy here ?
Correct our target to separate the L1/L2 EDAC from mc, and to maintain
both in separate drivers.
Thanks,
Hanna
Cheers,
Ben.
