Hello,
As part of an effort to bring suspend to RAM support to the Armada
3700 SoC (main target: ESPRESSObin board), there are small things to
do in the Armada 3700 peripherals clock driver:
* On this SoC, the PCIe controller gets fed by a gated clock in the
south bridge. This clock is missing in the current driver, patch 1
adds it.
* Because of a constraint in the PCI core, the resume function of a
PCIe controller driver must be run at an early stage
(->suspend/resume_noirq()), before the core tries to ->read/write()
in the PCIe registers to do more configuration. Hence, the PCIe
clock must be resumed before. This is enforced thanks to two
changes:
1/ Add device links to the clock framework. This enforce order in
the PM core: the clocks are resumed before the consumers. Series
has been posted, see [1].
2/ Even with the above feature, the clock's resume() callback is
called after the PCI controller's resume_noirq() callback. The
only way to fix this is to change the "priority" of the clock
suspend/resume callbacks. This is done in patch 2.
* The bindings are updated with the PCI clock in patch 4 while patch 3
is just a typo correction in the same file.
If there is anything unclear please feel free to ask.
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2018-November/614527.html
Thanks,
Miquèl
Changes in v2:
==============
* Rebased on top of v5.2-rc1.
* Added Rob's R-by tags.
* No change on the "change suspend/resume time" patch as, despite my
pings, I got no answer and IMHO the proposed approach is entirely
valid.
Miquel Raynal (4):
clk: mvebu: armada-37xx-periph: add PCIe gated clock
clk: mvebu: armada-37xx-periph: change suspend/resume time
dt-bindings: clk: armada3700: fix typo in SoC name
dt-bindings: clk: armada3700: document the PCIe clock
.../devicetree/bindings/clock/armada3700-periph-clock.txt | 5 +++--
drivers/clk/mvebu/armada-37xx-periph.c | 6 ++++--
2 files changed, 7 insertions(+), 4 deletions(-)
--
2.19.1
