Add nvmem-cells reference to cpu and fill the OPP table with all known
OPPs.
Signed-off-by: Leonard Crestez <leonard.crestez@xxxxxxx>
Acked-by: Viresh Kumar <viresh.kumar@xxxxxxxxxx>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 26 ++++++++++++++++++++++-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 6d635ba0904c..729376919d08 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -93,10 +93,12 @@
clocks = <&clk IMX8MQ_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
+ nvmem-cells = <&cpu_speed_grade>;
+ nvmem-cell-names = "speed_grade";
};
A53_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
@@ -143,18 +145,36 @@
opp-shared;
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <900000>;
+ /* Industrial only */
+ opp-supported-hw = <0xf>, <0x4>;
+ clock-latency-ns = <150000>;
+ };
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <900000>;
+ /* Consumer only */
+ opp-supported-hw = <0xe>, <0x3>;
clock-latency-ns = <150000>;
};
opp-1300000000 {
opp-hz = /bits/ 64 <1300000000>;
opp-microvolt = <1000000>;
+ opp-supported-hw = <0xc>, <0x7>;
+ clock-latency-ns = <150000>;
+ };
+
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <1000000>;
+ /* Consumer only but rely on speed grading */
+ opp-supported-hw = <0x8>, <0x7>;
clock-latency-ns = <150000>;
- opp-suspend;
};
};
pmu {
compatible = "arm,cortex-a53-pmu";
@@ -413,10 +433,14 @@
compatible = "fsl,imx8mq-ocotp", "syscon";
reg = <0x30350000 0x10000>;
clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
#address-cells = <1>;
#size-cells = <1>;
+
+ cpu_speed_grade: speed-grade@10 {
+ reg = <0x10 4>;
+ };
};
anatop: syscon@30360000 {
compatible = "fsl,imx8mq-anatop", "syscon";
reg = <0x30360000 0x10000>;
--
2.17.1
