The RZ/A2 has optional dedicated 48MHz crystal inputs, which adds a new
register setting when used.
Signed-off-by: Chris Brandt <chris.brandt@xxxxxxxxxxx>
---
drivers/phy/renesas/phy-rcar-gen3-usb2.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
index 1322185a00a2..218b32e458cb 100644
--- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
@@ -34,6 +34,7 @@
#define USB2_VBCTRL 0x60c
#define USB2_LINECTRL1 0x610
#define USB2_ADPCTRL 0x630
+#define USB2_PHYCLK_CTRL 0x644
/* INT_ENABLE */
#define USB2_INT_ENABLE_UCOM_INTEN BIT(3)
@@ -110,6 +111,7 @@ struct rcar_gen3_chan {
bool extcon_host;
bool is_otg_channel;
bool uses_otg_pins;
+ bool uses_usb_x1;
};
/*
@@ -391,6 +393,9 @@ static int rcar_gen3_phy_usb2_init(struct phy *p)
void __iomem *usb2_base = channel->base;
u32 val;
+ if (channel->uses_usb_x1)
+ writel(0x00000001, usb2_base + USB2_PHYCLK_CTRL);
+
/* Initialize USB2 part */
val = readl(usb2_base + USB2_INT_ENABLE);
val |= USB2_INT_ENABLE_UCOM_INTEN | rphy->int_enable_bits;
@@ -630,6 +635,9 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
}
}
+ if (of_property_read_bool(dev->of_node, "renesas,uses_usb_x1"))
+ channel->uses_usb_x1 = true;
+
/*
* devm_phy_create() will call pm_runtime_enable(&phy->dev);
* And then, phy-core will manage runtime pm for this device.
--
2.16.1
