> From: Anson Huang
> Sent: Monday, May 6, 2019 5:18 PM
> Subject: [PATCH 2/3] clk: imx8mm: add GPIO clocks to clock tree
>
> i.MX8MM has clock gate for each GPIO bank, add them into clock tree for
> GPIO driver to manage.
>
> Signed-off-by: Anson Huang <Anson.Huang@xxxxxxx>
Reviewed-by: Dong Aisheng <aisheng.dong@xxxxxxx>
Regards
Dong Aisheng
> ---
> drivers/clk/imx/clk-imx8mm.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
> index 1ef8438..733ca20 100644
> --- a/drivers/clk/imx/clk-imx8mm.c
> +++ b/drivers/clk/imx/clk-imx8mm.c
> @@ -590,6 +590,11 @@ static int __init imx8mm_clocks_init(struct
> device_node *ccm_node)
> clks[IMX8MM_CLK_ECSPI2_ROOT] = imx_clk_gate4("ecspi2_root_clk",
> "ecspi2", base + 0x4080, 0);
> clks[IMX8MM_CLK_ECSPI3_ROOT] = imx_clk_gate4("ecspi3_root_clk",
> "ecspi3", base + 0x4090, 0);
> clks[IMX8MM_CLK_ENET1_ROOT] = imx_clk_gate4("enet1_root_clk",
> "enet_axi", base + 0x40a0, 0);
> + clks[IMX8MM_CLK_GPIO1_ROOT] = imx_clk_gate4("gpio1_root_clk",
> "ipg_root", base + 0x40b0, 0);
> + clks[IMX8MM_CLK_GPIO2_ROOT] = imx_clk_gate4("gpio2_root_clk",
> "ipg_root", base + 0x40c0, 0);
> + clks[IMX8MM_CLK_GPIO3_ROOT] = imx_clk_gate4("gpio3_root_clk",
> "ipg_root", base + 0x40d0, 0);
> + clks[IMX8MM_CLK_GPIO4_ROOT] = imx_clk_gate4("gpio4_root_clk",
> "ipg_root", base + 0x40e0, 0);
> + clks[IMX8MM_CLK_GPIO5_ROOT] = imx_clk_gate4("gpio5_root_clk",
> +"ipg_root", base + 0x40f0, 0);
> clks[IMX8MM_CLK_GPT1_ROOT] = imx_clk_gate4("gpt1_root_clk", "gpt1",
> base + 0x4100, 0);
> clks[IMX8MM_CLK_I2C1_ROOT] = imx_clk_gate4("i2c1_root_clk", "i2c1",
> base + 0x4170, 0);
> clks[IMX8MM_CLK_I2C2_ROOT] = imx_clk_gate4("i2c2_root_clk", "i2c2",
> base + 0x4180, 0);
> --
> 2.7.4
