This patchset adds support for the gated clock controller found on most MIPS based Broadcom BCM63XX SoCs. The MIPS based BCM63XX SoCs have very little in common with the ARM based ones, so a separate driver is necessary. It's a simple register based controller, with one bit per clock, active high. Since BCM63XX/MIPS runs in big endian mode, the driver depends on the series "clk: make register endianness a run-time property", or more specifically on patch 3, "clk: gate: add explicit big endian support". Based on the clk-next branch. Jonas Gorski (3): devicetree: document the BCM63XX gated clock bindings clk: add BCM63XX gated clock controller driver MIPS: BMIPS: add clock controller nodes .../bindings/clock/brcm,bcm63xx-clocks.txt | 22 ++ arch/mips/boot/dts/brcm/bcm3368.dtsi | 12 +- arch/mips/boot/dts/brcm/bcm63268.dtsi | 12 +- arch/mips/boot/dts/brcm/bcm6328.dtsi | 6 + arch/mips/boot/dts/brcm/bcm6358.dtsi | 12 +- arch/mips/boot/dts/brcm/bcm6362.dtsi | 12 +- arch/mips/boot/dts/brcm/bcm6368.dtsi | 12 +- drivers/clk/bcm/Kconfig | 8 + drivers/clk/bcm/Makefile | 1 + drivers/clk/bcm/clk-bcm63xx-gate.c | 246 +++++++++++++++++++++ 10 files changed, 328 insertions(+), 15 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/brcm,bcm63xx-clocks.txt create mode 100644 drivers/clk/bcm/clk-bcm63xx-gate.c -- 2.13.2
