Hi Mark On Fri, Apr 4, 2014 at 3:13 AM, Mark Brown <broonie@xxxxxxxxxx> wrote: > On Thu, Apr 03, 2014 at 04:40:30PM +0530, Harini Katakam wrote: >> Add driver for Cadence SPI controller. This is used in Xilinx Zynq. > > I just reviewed a driver for "Zynq Quad SPI controller" from Punnaiah > Choudary Kalluri (CCed) which seems *very* similar to this one. Are > there opportunities for code sharing here (I'm not entirely sure the > hardware blocks are different, though I didn't check in detail). > Thanks for the review. QSPI is a Xilinx IP built on top of cadence SPI with considerable functional changes. As explained in the QSPI patch, there are three configurations QSPI supports : - A single flash device connected with 1 CS and 4 IO lines - Two flash devices connected over two separate sets of 4 IO lines and two CS lines which are driven together. - Two flash devices connected with two separate CS line and one common set of 4 IO lines. This first set of QSPI patches is only for the single flash configuration. As the next two configurations follow, QSPI driver will differ from SPI even more. That's why it might be better to have two separate drivers. It will avoid a lot of "if spi/ if qspi" checks. I will send an RFC with proposed changes for all QSPI configurations. Also, I've replied to your comments on the QSPI driver. (The QSPI driver already addresses the comments for SPI v1) Except in two places where the comment was only applicable to QSPI driver, the replies hold good for both SPI and QSPI drivers. If you would like to continue the discussion on that thread, I'm ok with it. FYI, I'll be sending the next versions for both drivers after further discussion concludes. Regards, Harini -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
