On Wed, 17 Apr 2019 at 06:26, Anand Moon <linux.amoon@xxxxxxxxx> wrote: > > Hi Krzysztof, > > On Tue, 16 Apr 2019 at 15:49, Krzysztof Kozlowski <krzk@xxxxxxxxxx> wrote: > > > > On Mon, 15 Apr 2019 at 14:24, Anand Moon <linux.amoon@xxxxxxxxx> wrote: > > > Cache Coherent Interface (CCI) among Cortex-A15 and Cortex-A7, G2D, G3D and SSS > > > > > > Level 0 > CPU blocks such as Cortex-A15 (CA15), Cortex-A7 (CA7) are > > > joined as the member of Level 0 CCI bus > > > > > > Level 1 > Display engine block (DISP) and 2D graphic engines (G2D) are > > > directly connected to Level 1. > > > DISP, MDMA, SSS. > > > > > > Level 2 > While all the other IP is connected to Level 1 bus via Level 2 bus > > > G3D, MSCL, MFC, ISP, JPEG/Rotator/DMA/PERI, NAND/SD/EMMC. > > > > > > So my question is the mapped with the cci ip block correct. > > > Level 0 (cci_control0) > > > Level 1 (cci_control1) > > > Level 2 (cci_control1) > > > > Hi Anand, > > > > I do not understand the question - what is mapped with correctly or not? > > > > Best regards, > > Krzysztof > > Following the https://www.kernel.org/doc/Documentation/devicetree/bindings/arm/cci.txt > CCI node linked to CPU and DMA nodes for example. > > On this line below diagram from Exynos 5422 UM show various IP block > linked to CCI level. > Below image just elaborate overall architecture of Exynos 5422 CCI. > > [0] https://imgur.com/gallery/0xJSwGQ > > So we should map the various IP block to corresponding CCI level. Willy's patch did not touch cci_control{0,1} nor any other CCI levels so I do not get what are you commenting. As for other CCI ports - we do not define them and I do not see any users of device CCI API (cci_enable_port_by_device() and cci_disable_port_by_device()). But feel free to propose patches changing this. In general - it is easier to discuss if you show the code/patch, not talk about some theoretical change. Best regards, Krzysztof
