Hi,
On Wed, Apr 10, 2019 at 03:02:12PM +0200, Lucas Stach wrote:
> Hi Guido,
>
> Am Montag, den 08.04.2019, 15:45 +0200 schrieb Guido Günther:
> > Hi,
> > On Mon, Apr 08, 2019 at 03:07:29PM +0200, Guido Günther wrote:
> > > Hi Lucas,
> > > On Thu, Apr 04, 2019 at 06:52:11PM +0200, Lucas Stach wrote:
> > > > This enables the Vivante GC7000L GPU on the i.MX8MQ SoC.
> > > >
> > > > > > > Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
> > > > ---
> > > > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 22 ++++++++++++++++++++++
> > > > 1 file changed, 22 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > index 4300781558f6..79d418b4f585 100644
> > > > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > @@ -792,6 +792,28 @@
> > > > > > > };
> > > > > > > };
> > > >
> > > > > > > > > > + gpu: gpu@38000000 {
> > > > > > > + compatible = "vivante,gc";
> > > > > > > + reg = <0x38000000 0x40000>;
> > > > > > > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
> > > > > > > + <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
> > > > > > > + <&clk IMX8MQ_CLK_GPU_AXI>,
> > > > > > > + <&clk IMX8MQ_CLK_GPU_AHB>;
> > > > > > > + clock-names = "core", "shader", "bus", "reg";
> > > > > > > + assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
> > > > > > > + <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
> > > > > > > + <&clk IMX8MQ_CLK_GPU_AXI>,
> > > > > > > + <&clk IMX8MQ_CLK_GPU_AHB>;
> > > > > > > + assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
> > > > > > > + <&clk IMX8MQ_GPU_PLL_OUT>,
> > > > > > > + <&clk IMX8MQ_GPU_PLL_OUT>,
> > > > > > > + <&clk IMX8MQ_GPU_PLL_OUT>;
> > > > > > > + assigned-clock-rates = <800000000>, <800000000>,
> > > > > > > + <800000000>, <800000000>;
> > > > > > > + power-domains = <&pgc_gpu>;
> > > > + };
> > >
> > > Reviewed-by: Guido Günther <agx@xxxxxxxxxxx>
> >
> > On a second thought should this have a
> >
> > status = "disabled";
>
> I disagree. This is a SoC internal peripheral, that has no board level
> dependencies other than the voltage rail being connected, so it's fine
> to have the node enabled on all systems. This is consistent with what
> we did on all previous i.MX SoC DTs.
Makes sense.
Reviewed-by: Guido Günther <agx@xxxxxxxxxxx>
Cheers,
-- Guido
