On Mon, Apr 08, 2019 at 09:41:47AM +0200, Miquel Raynal wrote: > In the current state, A33 NAND controllers use PIO during > transfers. Throughput can be increased thanks to the use of DMA > (mostly during reads, because of the ECC pipelining feature). > > Besides the usual addition of DMA DT properties, because the A33 > NAND DMA handling is different than for older SoCs, we must also > update the compatible which has recently been introduced for this > purpose. > > Signed-off-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx> Applied, thanks! The rest is Acked-by: Maxime Ripard <maxime.ripard@xxxxxxxxxxx> Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
Attachment:
signature.asc
Description: PGP signature
