In the current state, A33 NAND controllers use PIO during
transfers. Throughput can be increased thanks to the use of DMA
(mostly during reads, because of the ECC pipelining feature).
Besides the usual addition of DMA DT properties, because the A33
NAND DMA handling is different than for older SoCs, we must also
update the compatible which has recently been introduced for this
purpose.
Signed-off-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx>
---
Changes in v2:
* Use 'A33' in the commit log instead of sun8i.
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 14a7d0288b45..f928b4bceb22 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -162,11 +162,13 @@
};
nfc: nand@1c03000 {
- compatible = "allwinner,sun4i-a10-nand";
+ compatible = "allwinner,sun8i-a33-nand-controller";
reg = <0x01c03000 0x1000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
clock-names = "ahb", "mod";
+ dmas = <&dma 5>;
+ dma-names = "rxtx";
resets = <&ccu RST_BUS_NAND>;
reset-names = "ahb";
pinctrl-names = "default";
--
2.19.1
