>-----Original Message-----
>From: Vladimir Oltean
>Sent: Monday, March 25, 2019 11:31 AM
>To: shawnguo@xxxxxxxxxx; Leo Li <leoyang.li@xxxxxxx>; Claudiu Manoil
><claudiu.manoil@xxxxxxx>
>Cc: robh+dt@xxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx;
>devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx;
>netdev@xxxxxxxxxxxxxxx; davem@xxxxxxxxxxxxx; Vladimir Oltean
><vladimir.oltean@xxxxxxx>
>Subject: [PATCH] ARM: dts: ls1021: Fix SGMII PCS link remaining down after PHY
>disconnect
>
>Each eTSEC MAC has its own TBI (SGMII) PCS and private MDIO bus.
>But due to a DTS oversight, both SGMII-compatible MACs of the LS1021 SoC are
>pointing towards the same internal PCS. Therefore nobody is controlling the
>internal PCS of eTSEC0.
>
>Upon initial ndo_open, the SGMII link is ok by virtue of U-boot initialization. But
>upon an ifdown/ifup sequence, the code path from ndo_open -> init_phy ->
>gfar_configure_serdes does not get executed for the PCS of eTSEC0 (and is
>executed twice for MAC eTSEC1). So the SGMII link remains down for eTSEC0.
>On the LS1021A-TWR board, to signal this failure condition, the PHY driver keeps
>printing
>'803x_aneg_done: SGMII link is not ok'.
>
>Fixes: 055223d4d22d ("ARM: dts: ls1021a: Enable the eTSEC ports on QDS and
>TWR")
>Signed-off-by: Vladimir Oltean <vladimir.oltean@xxxxxxx>
Reviewed-by: Claudiu Manoil <claudiu.manoil@xxxxxxx>
