On 04/03/2019 14:42, Laurent Pinchart wrote: > Hi Jyri, > > On Wed, Feb 27, 2019 at 11:54:18PM +0200, Jyri Sarha wrote: >> Changes since first version: >> - Moved reviewed patches to front: >> - drm/bridge: sii902x: add input_bus_flags >> - drm/bridge: sii902x: Set output mode to HDMI or DVI according to EDID >> - drm/bridge: sii902x: pixel clock unit is 10kHz instead of 1kHz >> - Added a new fix: >> - drm/bridge: sii902x: Select I2C_MUX >> - Applied some review suggestions to >> - drm/bridge: sii902x: Implement HDMI audio support >> - use clock-names property to name mclk >> - move comment describing added mutex to struct sii902x and improve it >> - cleanup sii902x_mute() >> - cleanup sii902x_select_mclk_div() >> - fix condition for checking ENABLE_BIT from i2s_fifo_routing in >> sii902x_audio_codec_init() >> >> Still to do >> >> - Agree on i2s wires to HDMI audio fifo routing in dts. >> >> The current scheme is quite straight forward, but there is maybe >> there is even more straight forward solutions like: >> >> audio-fifo-enable = <1 1 1 1>; >> audio-i2s-pin-to-fifo = <0 1 2 3>; >> >> Meaning that all fifos are enabled and SD0 is routed to fifo 0, SD1 >> to fifo 1, etc. I am not sure if the channel swap functionality >> should show in dts binding. > Please forgive my lack of audio knowledge, but it this a system > description that should be encoded in DT, or a policy that should be > handled purely in software (either fully inside the kernel or with the > help of userspace) ? > This property describes how many i2s wires are connected to sii902x and in what order, so I think it belongs to DTS. One might of course wonder why anybody would put the i2s wires to any other order than 0 <-> 0, 1 <-> 1, 2 <-> 2, and 3 <-> 3, but then a again I've seen weirder board designs. Best regards, Jyri -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
