On 19-02-28 22:20:32, Shawn Guo wrote: > On Fri, Feb 15, 2019 at 06:07:24PM +0000, Abel Vesa wrote: > > Add the 0.8GHz and 1GHz opps. According to the datasheet: > > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.nxp.com%2Fdocs%2Fen%2Fdata-sheet%2FIMX8MDQLQIEC.pdf&data=02%7C01%7Cabel.vesa%40nxp.com%7C05d898b625824204bb3908d69d880aaf%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C636869604952370425&sdata=yDuM%2ByO%2F9twQ3cXTR%2FkCSSfxOMm015qG%2FfBSFZC91SQ%3D&reserved=0 > > section 3.1.3 Operating ranges. > > > > The 0.8GHz opp runs in nominal mode with the regulator set to 0.9V. > > The 1GHz runs in overdrive mode with the regulator set to 1V. > > > > Signed-off-by: Abel Vesa <abel.vesa@xxxxxxx> > > --- > > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 23 +++++++++++++++++++++++ > > 1 file changed, 23 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > index 1a89062..ebdec9e 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > @@ -91,6 +91,7 @@ > > clocks = <&clk IMX8MQ_CLK_ARM>; > > enable-method = "psci"; > > next-level-cache = <&A53_L2>; > > + operating-points-v2 = <&a53_0_opp_table>; > > }; > > > > A53_1: cpu@1 { > > @@ -101,6 +102,7 @@ > > clocks = <&clk IMX8MQ_CLK_ARM>; > > enable-method = "psci"; > > next-level-cache = <&A53_L2>; > > + operating-points-v2 = <&a53_0_opp_table>; > > }; > > > > A53_2: cpu@2 { > > @@ -111,6 +113,7 @@ > > clocks = <&clk IMX8MQ_CLK_ARM>; > > enable-method = "psci"; > > next-level-cache = <&A53_L2>; > > + operating-points-v2 = <&a53_0_opp_table>; > > }; > > > > A53_3: cpu@3 { > > @@ -121,6 +124,7 @@ > > clocks = <&clk IMX8MQ_CLK_ARM>; > > enable-method = "psci"; > > next-level-cache = <&A53_L2>; > > + operating-points-v2 = <&a53_0_opp_table>; > > }; > > > > A53_L2: l2-cache0 { > > @@ -666,6 +670,25 @@ > > status = "disabled"; > > }; > > > > + > > + a53_0_opp_table: opp-table { > > What's the point of having '0' in the label name, considering it's > actually referred by all CPU nodes? > Good catch. Will remove and resend. Thanks. > Shawn > > > + compatible = "operating-points-v2"; > > + opp-shared; > > + > > + opp-800000000 { > > + opp-hz = /bits/ 64 <800000000>; > > + opp-microvolt = <900000>; > > + clock-latency-ns = <150000>; > > + }; > > + > > + opp-1000000000 { > > + opp-hz = /bits/ 64 <1000000000>; > > + opp-microvolt = <1000000>; > > + clock-latency-ns = <150000>; > > + opp-suspend; > > + }; > > + }; > > + > > gic: interrupt-controller@38800000 { > > compatible = "arm,gic-v3"; > > reg = <0x38800000 0x10000>, /* GIC Dist */ > > -- > > 2.7.4 > > > > > > _______________________________________________ > > linux-arm-kernel mailing list > > linux-arm-kernel@xxxxxxxxxxxxxxxxxxx > > https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Flists.infradead.org%2Fmailman%2Flistinfo%2Flinux-arm-kernel&data=02%7C01%7Cabel.vesa%40nxp.com%7C05d898b625824204bb3908d69d880aaf%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C636869604952370425&sdata=HD1WvWQJGR319rM5OrQRXRLU2zEuHzEeLMkq3vbi3OA%3D&reserved=0
