Add lsio lpcg clocks
Cc: Rob Herring <robh+dt@xxxxxxxxxx>
Cc: Mark Rutland <mark.rutland@xxxxxxx>
Cc: devicetree@xxxxxxxxxxxxxxx
Cc: Shawn Guo <shawnguo@xxxxxxxxxx>
Cc: Sascha Hauer <kernel@xxxxxxxxxxxxxx>
Cc: Fabio Estevam <fabio.estevam@xxxxxxx>
Signed-off-by: Dong Aisheng <aisheng.dong@xxxxxxx>
---
arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 107 +++++++++++++++++++++++-
1 file changed, 106 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
index 5c4c2fb..cf9223d 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
@@ -132,7 +132,112 @@ lsio_subsys: bus@5d000000 {
clock-output-names = "pwm7_clk";
};
- lsio_lpcg: clock-controller@5d400000 {
+ /* LPCG clocks */
+ pwm0_lpcg: clock-controller@5d400000 {
+ reg = <0x5d400000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&pwm0_clk>, <&pwm0_clk>, <&pwm0_clk>,
+ <&lsio_bus_clk>, <&pwm0_clk>;
+ bit-offset = <0 4 16 20 24>;
+ clock-output-names = "pwm0_lpcg_ipg_clk",
+ "pwm0_lpcg_ipg_hf_clk",
+ "pwm0_lpcg_ipg_s_clk",
+ "pwm0_lpcg_ipg_slv_clk",
+ "pwm0_lpcg_ipg_mstr_clk";
+ };
+
+ pwm1_lpcg: clock-controller@5d410000 {
+ reg = <0x5d410000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&pwm1_clk>, <&pwm1_clk>, <&pwm1_clk>,
+ <&lsio_bus_clk>, <&pwm1_clk>;
+ bit-offset = <0 4 16 20 24>;
+ clock-output-names = "pwm1_lpcg_ipg_clk",
+ "pwm1_lpcg_ipg_hf_clk",
+ "pwm1_lpcg_ipg_s_clk",
+ "pwm1_lpcg_ipg_slv_clk",
+ "pwm1_lpcg_ipg_mstr_clk";
+ };
+
+ pwm2_lpcg: clock-controller@5d420000 {
+ reg = <0x5d420000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&pwm2_clk>, <&pwm2_clk>, <&pwm2_clk>,
+ <&lsio_bus_clk>, <&pwm2_clk>;
+ bit-offset = <0 4 16 20 24>;
+ clock-output-names = "pwm2_lpcg_ipg_clk",
+ "pwm2_lpcg_ipg_hf_clk",
+ "pwm2_lpcg_ipg_s_clk",
+ "pwm2_lpcg_ipg_slv_clk",
+ "pwm2_lpcg_ipg_mstr_clk";
+ };
+
+ pwm3_lpcg: clock-controller@5d430000 {
+ reg = <0x5d430000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&pwm3_clk>, <&pwm3_clk>, <&pwm3_clk>,
+ <&lsio_bus_clk>, <&pwm3_clk>;
+ bit-offset = <0 4 16 20 24>;
+ clock-output-names = "pwm3_lpcg_ipg_clk",
+ "pwm3_lpcg_ipg_hf_clk",
+ "pwm3_lpcg_ipg_s_clk",
+ "pwm3_lpcg_ipg_slv_clk",
+ "pwm3_lpcg_ipg_mstr_clk";
+ };
+
+ pwm4_lpcg: clock-controller@5d440000 {
+ reg = <0x5d440000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&pwm4_clk>, <&pwm4_clk>, <&pwm4_clk>,
+ <&lsio_bus_clk>, <&pwm4_clk>;
+ bit-offset = <0 4 16 20 24>;
+ clock-output-names = "pwm4_lpcg_ipg_clk",
+ "pwm4_lpcg_ipg_hf_clk",
+ "pwm4_lpcg_ipg_s_clk",
+ "pwm4_lpcg_ipg_slv_clk",
+ "pwm4_lpcg_ipg_mstr_clk";
+ };
+
+ pwm5_lpcg: clock-controller@5d450000 {
+ reg = <0x5d450000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&pwm5_clk>, <&pwm5_clk>, <&pwm5_clk>,
+ <&lsio_bus_clk>, <&pwm5_clk>;
+ bit-offset = <0 4 16 20 24>;
+ clock-output-names = "pwm5_lpcg_ipg_clk",
+ "pwm5_lpcg_ipg_hf_clk",
+ "pwm5_lpcg_ipg_s_clk",
+ "pwm5_lpcg_ipg_slv_clk",
+ "pwm5_lpcg_ipg_mstr_clk";
+ };
+
+ pwm6_lpcg: clock-controller@5d460000 {
+ reg = <0x5d460000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&pwm6_clk>, <&pwm6_clk>, <&pwm6_clk>,
+ <&lsio_bus_clk>, <&pwm6_clk>;
+ bit-offset = <0 4 16 20 24>;
+ clock-output-names = "pwm6_lpcg_ipg_clk",
+ "pwm6_lpcg_ipg_hf_clk",
+ "pwm6_lpcg_ipg_s_clk",
+ "pwm6_lpcg_ipg_slv_clk",
+ "pwm6_lpcg_ipg_mstr_clk";
+ };
+
+ pwm7_lpcg: clock-controller@5d470000 {
+ reg = <0x5d470000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&pwm7_clk>, <&pwm7_clk>, <&pwm7_clk>,
+ <&lsio_bus_clk>, <&pwm7_clk>;
+ bit-offset = <0 4 16 20 24>;
+ clock-output-names = "pwm7_lpcg_ipg_clk",
+ "pwm7_lpcg_ipg_hf_clk",
+ "pwm7_lpcg_ipg_s_clk",
+ "pwm7_lpcg_ipg_slv_clk",
+ "pwm7_lpcg_ipg_mstr_clk";
+ };
+
+ lsio_lpcg: clock-controller-legacy@5d400000 {
reg = <0x5d400000 0x400000>;
#clock-cells = <1>;
};
--
2.7.4
