Add adma lpcg clocks
Cc: Rob Herring <robh+dt@xxxxxxxxxx>
Cc: Mark Rutland <mark.rutland@xxxxxxx>
Cc: devicetree@xxxxxxxxxxxxxxx
Cc: Shawn Guo <shawnguo@xxxxxxxxxx>
Cc: Sascha Hauer <kernel@xxxxxxxxxxxxxx>
Cc: Fabio Estevam <fabio.estevam@xxxxxxx>
Signed-off-by: Dong Aisheng <aisheng.dong@xxxxxxx>
---
arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi | 73 +++++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
index 5f0e9e3..c7adeba 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
@@ -146,6 +146,79 @@ adma_subsys: bus@59000000 {
clock-output-names = "uart3_clk";
};
+ /* LPCG clocks */
+ uart0_lpcg: clock-controller@5a460000 {
+ reg = <0x5a460000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&uart0_clk>, <&adma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "uart0_lpcg_baud_clk",
+ "uart0_lpcg_ipg_clk";
+ };
+
+ uart1_lpcg: clock-controller@5a470000 {
+ reg = <0x5a470000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&uart1_clk>, <&adma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "uart1_lpcg_baud_clk",
+ "uart1_lpcg_ipg_clk";
+ };
+
+ uart2_lpcg: clock-controller@5a480000 {
+ reg = <0x5a480000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&uart2_clk>, <&adma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "uart2_lpcg_baud_clk",
+ "uart2_lpcg_ipg_clk";
+ };
+
+ uart3_lpcg: clock-controller@5a490000 {
+ reg = <0x5a490000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&uart3_clk>, <&adma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "uart3_lpcg_baud_clk",
+ "uart3_lpcg_ipg_clk";
+ };
+
+ i2c0_lpcg: clock-controller@5ac00000 {
+ reg = <0x5ac00000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&i2c0_clk>, <&adma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "i2c0_lpcg_clk",
+ "i2c0_lpcg_ipg_clk";
+ };
+
+ i2c1_lpcg: clock-controller@5ac10000 {
+ reg = <0x5ac10000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&i2c1_clk>, <&adma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "i2c1_lpcg_clk",
+ "i2c1_lpcg_ipg_clk";
+ };
+
+ i2c2_lpcg: clock-controller@5ac20000 {
+ reg = <0x5ac20000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&i2c2_clk>, <&adma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "i2c2_lpcg_clk",
+ "i2c2_lpcg_ipg_clk";
+ };
+
+ i2c3_lpcg: clock-controller@5ac30000 {
+ reg = <0x5ac30000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&i2c3_clk>, <&adma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "i2c3_lpcg_clk",
+ "i2c3_lpcg_ipg_clk";
+ };
+
adma_lpcg: clock-controller@59000000 {
reg = <0x59000000 0x2000000>;
#clock-cells = <1>;
--
2.7.4
