On Thu, Jan 24, 2019 at 01:22:45PM +0000, Aisheng Dong wrote: > Add a53 and a72 clock id, as there's still no users, we update > IMX_LSIO_MEM_CLK base to start from 6 to allow a53 and a72 clock > id to be continued with a35 clk. > > Cc: Stephen Boyd <sboyd@xxxxxxxxxx> > Cc: Rob Herring <robh+dt@xxxxxxxxxx> > Cc: devicetree@xxxxxxxxxxxxxxx > Cc: Shawn Guo <shawnguo@xxxxxxxxxx> > Cc: Sascha Hauer <kernel@xxxxxxxxxxxxxx> > Cc: Fabio Estevam <fabio.estevam@xxxxxxx> > Cc: Michael Turquette <mturquette@xxxxxxxxxxxx> > Signed-off-by: Dong Aisheng <aisheng.dong@xxxxxxx> > --- > v1->v2: > * change cpu clock to cpu cluster clock per Rob's suggestion > --- > include/dt-bindings/clock/imx8-clock.h | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/include/dt-bindings/clock/imx8-clock.h b/include/dt-bindings/clock/imx8-clock.h > index b149e63..dcce744 100644 > --- a/include/dt-bindings/clock/imx8-clock.h > +++ b/include/dt-bindings/clock/imx8-clock.h > @@ -14,10 +14,12 @@ > /* CPU */ > #define IMX_A35_CLK 1 > #define IMX_CPU_CLUSTER_A35_CLK 1 > +#define IMX_CPU_CLUSTER_A53_CLK 2 > +#define IMX_CPU_CLUSTER_A72_CLK 3 I still don't get this. How many clock outputs does the clock controller have for CPUs? If 3, then this is correct. If it's the same clock controller bits across different SoCs, then just name it something like IMX_CPU_CLUSTER_CLK and reuse the same ID. > /* LSIO SS */ > -#define IMX_LSIO_MEM_CLK 2 > -#define IMX_LSIO_BUS_CLK 3 > +#define IMX_LSIO_MEM_CLK 6 > +#define IMX_LSIO_BUS_CLK 7 Changing numbering is not good, but I guess it's early for imx8. > #define IMX_LSIO_PWM0_CLK 10 > #define IMX_LSIO_PWM1_CLK 11 > #define IMX_LSIO_PWM2_CLK 12 > -- > 2.7.4 >
