On Fri, Feb 8, 2019 at 12:44 PM Fabio Estevam <festevam@xxxxxxxxx> wrote:
>
> Hi Frank,
>
> On Fri, Feb 8, 2019 at 4:32 PM Frank Li <frank.li@xxxxxxx> wrote:
> >
> > Add ddr performance monitor
> >
> > Signed-off-by: Frank Li <Frank.Li@xxxxxxx>
> > ---
> > arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 7 +++++++
> > 1 file changed, 7 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > index 4c3dd95..243d7b3 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > @@ -79,6 +79,13 @@
> > interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> > };
> >
> > + ddr_pmu0: ddr_pmu@5c020000 {
> > + compatible = "fsl,imx8-ddr-pmu";
> > + reg = <0x0 0x5c020000 0x0 0x10000>;
>
> In mainline tree this should be:
>
> reg = <0x5c020000 0x10000>;
If it is true if under subsystem node. ddr pmu is the same level as
GIC. So address should be 64bit
gic: interrupt-controller@51a00000 {
compatible = "arm,gic-v3";
reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
<0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base +
SGI_base) */
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
best regards
Frank Li
