> -----Original Message----- > From: Pankaj Bansal > Sent: Tuesday, February 5, 2019 4:15 AM > To: Leo Li <leoyang.li@xxxxxxx>; Rob Herring <robh+dt@xxxxxxxxxx>; Mark > Rutland <mark.rutland@xxxxxxx> > Cc: linuxppc-dev@xxxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; > open list : OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS > <devicetree@xxxxxxxxxxxxxxx>; Pankaj Bansal <pankaj.bansal@xxxxxxx> > Subject: [PATCH v4 1/2] dt-bindings: soc: fsl: Document Qixis FPGA usage > > an FPGA-based system controller, called “Qixis”, which > manages several critical system features, including: > • Reset sequencing > • Power supply configuration > • Board configuration > • hardware configuration > > The qixis registers are accessible over one or more system-specific > interfaces, typically I2C, JTAG or an embedded processor. In theory the on-board FPGA is not part of the SoC. The Qixis device has been defined previously in Documentation/devicetree/bindings/board/fsl-board.txt file. Although normally board bindings are defined in architecture specific binding folders, this is a good place for board related stuff used across multiple architectures. You can update the existing binding if needed. > > Signed-off-by: Pankaj Bansal <pankaj.bansal@xxxxxxx> > --- > > Notes: > V4: > - No Change > V3: > - Added boardname based compatible field in bindings > - Added bindings for MMIO based FPGA > V2: > - No change > > .../bindings/soc/fsl/qixis_ctrl.txt | 53 ++++++++++++++++++ > 1 file changed, 53 insertions(+) > > diff --git a/Documentation/devicetree/bindings/soc/fsl/qixis_ctrl.txt > b/Documentation/devicetree/bindings/soc/fsl/qixis_ctrl.txt > new file mode 100644 > index 000000000000..5d510df14be8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/fsl/qixis_ctrl.txt > @@ -0,0 +1,53 @@ > +* QIXIS FPGA block > + > +an FPGA-based system controller, called “Qixis”, which > +manages several critical system features, including: > +• Configuration switch monitoring > +• Power on/off sequencing > +• Reset sequencing > +• Power supply configuration > +• Board configuration > +• hardware configuration > +• Background power data collection (DCM) > +• Fault monitoring > +• RCW bypass SRAM (replace flash RCW with internal RCW) (NOR only) > +• Dedicated functional validation blocks (POSt/IRS, triggered event, and so > on) > +• I2C master for remote board control even with no DUT available > + > +The qixis registers are accessible over one or more system-specific > interfaces, > +typically I2C, JTAG or an embedded processor. > + > +FPGA connected to I2C: > +Required properties: > + > + - compatible: should be a board-specific string followed by a string > + indicating the type of FPGA. Example: > + "fsl,<board>-fpga", "fsl,fpga-qixis-i2c" > + - reg : i2c address of the qixis device. > + > +Example (LX2160A-QDS): > + /* The FPGA node */ > + fpga@66 { > + compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c"; > + reg = <0x66>; > + #address-cells = <1>; > + #size-cells = <0>; > + } > + > +* Freescale on-board FPGA > + > +This is the memory-mapped registers for on board FPGA. > + > +Required properties: > +- compatible: should be a board-specific string followed by a string > + indicating the type of FPGA. Example: > + "fsl,<board>-fpga", "fsl,fpga-qixis" > +- reg: should contain the address and the length of the FPGA register set. > + > +Example (LS2080A-RDB): > + > + cpld@3,0 { > + compatible = "fsl,ls2080ardb-fpga", "fsl,fpga-qixis"; > + reg = <0x3 0 0x10000>; > + }; > + > -- > 2.17.1