On 02/01/2019 09:57 AM, Boris Brezillon wrote: > On Fri, 1 Feb 2019 07:07:40 +0000 > <Tudor.Ambarus@xxxxxxxxxxxxx> wrote: > >>> >>>> #define QSPI_IFR_TFRTYP_MASK GENMASK(13, 12) >>>> #define QSPI_IFR_TFRTYP_TRSFR_READ (0 << 12) >>>> #define QSPI_IFR_TFRTYP_TRSFR_READ_MEM (1 << 12) >>> >>> Looks like the read/write flag is on bit 13. Can we just add >> >> for sama5d2 only > > Feel free to prefix macros with the SoC name to make it clear: > > #define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13) agreed > cut >>>> +#define QSPI_IFR_APBTFRTYP_READ BIT(24) > > And this one would be > > define QSPI_IFR_SAM9X60_READ_TRSFR BIT(24) I prefer letting this bit named as in the datasheet, QSPI_IFR_APBTFRTYP_READ, and change it if future versions of the IP will modify its sense. It is a READ transfer done on APB, it is more generic this way. If you have a strong opinion on this, please let me know. ta
