Enable Qualcomm UFS controllers to expose the PHY reset via a reset controller. Signed-off-by: Evan Green <evgreen@xxxxxxxxxxxx> --- Fixing up this aspect of it made me notice that this patch [1] hasn't landed yet. It really ought to. [1] https://lore.kernel.org/lkml/20181012213926.253765-1-dianders@xxxxxxxxxxxx/T/#u Changes in v2: None Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt index 8cf59452c6756..e2460b666ae45 100644 --- a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt +++ b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt @@ -47,6 +47,8 @@ Optional properties: -lanes-per-direction : number of lanes available per direction - either 1 or 2. Note that it is assume same number of lanes is used both directions at once. If not specified, default is 2 lanes per direction. +- #reset-cells : Must be <1> for Qualcomm UFS controllers that expose + PHY reset from the UFS controller. - resets : reset node register - reset-names : describe reset node register, the "rst" corresponds to reset the whole UFS IP. @@ -76,4 +78,5 @@ Example: reset-names = "rst"; phys = <&ufsphy1>; phy-names = "ufsphy"; + #reset-cells = <1>; }; -- 2.18.1
