On 20/01/19 8:58 PM, Tudor.Ambarus@xxxxxxxxxxxxx wrote: > Vignesh, > > On 01/20/2019 04:56 PM, Tudor.Ambarus@xxxxxxxxxxxxx wrote: >> Looks good. > > one more thing: in cqspi_read_setup() I see that the dummy cycles are adjusted > if (f_pdata->inst_width != CQSPI_INST_TYPE_QUAD). > > Should you adjust the dummy cycles for octo too? Driver does not claim support for SNOR_HWCAPS_PP_4_4_4 mode or SNOR_HWCAPS_PP_8_8_8 mode. Therefore inst_width is always be CQSPI_INST_TYPE_SINGLE (cqspi_set_protocol() always sets inst_width and addr_width to CQSPI_INST_TYPE_SINGLE). Code to support 4_4_4 or 8_8_8 mode is incomplete in the driver. Also, using mode bits to satisfy dummy clk cycles does not seem right. My guess is driver is broken, if inst_width is indeed CQSPI_INST_TYPE_QUAD as we end up sending additional 8 dummy clock cycles over what is asked in nor->read_dummy. I will plan to fix these as part of moving driver over to spi-mem. But above code should not impact 1-1-8 mode support. > I tried to find a datasheet for the controller, without success though ... > You can find Octal SPI controller datasheet in AM65x SoC TRM here: http://www.ti.com/lit/ug/spruid7b/spruid7b.pdf Page 9449: 12.3.2 Octal Serial Peripheral Interface (OSPI) -- Regards Vignesh
