On Wed, Mar 19, 2014 at 1:41 PM, Thomas Gleixner <tglx@xxxxxxxxxxxxx> wrote: > On Wed, 19 Mar 2014, Maxime Ripard wrote: > >> On Wed, Mar 19, 2014 at 12:13:56PM +0100, Thomas Gleixner wrote: >> > On Sat, 15 Mar 2014, Carlo Caione wrote: >> > >> > > Allwinner A20/A31 SoCs have a special interrupt controller for managing NMI. >> > > Three register are present to (un)mask, control and acknowledge NMI. >> > > These two patches add a new irqchip driver in cascade with GIC. >> > >> > If I get an ack for the DT parts, I'll pick it up. >> >> I had some comments on it, so Carlo will probably resubmit it. > > That's the resubmit as far as I can tell. I'll submit a v7 addressing the Maxime's comments on DT part. Regards, -- Carlo Caione -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
