On Wed, Mar 19, 2014 at 12:13:56PM +0100, Thomas Gleixner wrote: > On Sat, 15 Mar 2014, Carlo Caione wrote: > > > Allwinner A20/A31 SoCs have a special interrupt controller for managing NMI. > > Three register are present to (un)mask, control and acknowledge NMI. > > These two patches add a new irqchip driver in cascade with GIC. > > If I get an ack for the DT parts, I'll pick it up. I had some comments on it, so Carlo will probably resubmit it. -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
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