On Tue, Dec 18, 2018 at 12:09 PM Leonard Crestez <leonard.crestez@xxxxxxx> wrote: > > On 12/18/2018 5:15 PM, Rob Herring wrote: > > On Mon, Dec 17, 2018 at 08:07:02PM -0800, Andrey Smirnov wrote: > >> Add code needed to support i.MX8MQ variant. > >> > >> Signed-off-by: Andrey Smirnov <andrew.smirnov@xxxxxxxxx> > >> Reviewed-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx> > > >> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt > >> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt > >> > >> +Additional required properties for imx8mq-pcie: > >> +- fsl,controller-id: Logical ID of a given PCIE controller. PCIE1 is 0, PCIE2 is 1; > >> + > > > > Remove this. > > > > If GPR register offset is what you need, then put that into DT. > > Typically, we'd have a property with iomuxc phandle and offset. > > This series initially added explicit offsets but I suggested a single > "controller-id" because: > * There are multiple bit and byte offsets > * Other imx8 SOCs also have 2x pcie with other bit/byte offsets > > Hiding this behind a compatible string and single "controller-id" seem > preferable to elaborating register maps in dt bindings. It also makes > upgrades simpler: if features are added which use other bits there is no > need to describe them in DT and deal with compatibility headaches. You don't have to describe all bit and byte offsets. Once you know 1, you can derive all the others. In fact, it doesn't have to be a register field at all, just provide whatever identifier you need: <$syscon 0> and <&syscon 1> Rob
