Add the compatible and allow the driver to also not set any crtc input
on socs that only have one vop. While that was already possible
because the driver checked against the grf-reg being 0, make that
var an int as "0x0" is a valid grf address itself. So standardize
on -1 for "no setting needed".
The dp controller behaves similar to the one found on rk3288, so we
don't add a new chip_type to not overly pollute the bridge driver.
Signed-off-by: Heiko Stuebner <heiko@xxxxxxxxx>
---
.../display/rockchip/analogix_dp-rockchip.txt | 1 +
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 17 +++++++++++++----
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
index 43561584c13a..d0f7a1292355 100644
--- a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
@@ -3,6 +3,7 @@ Rockchip RK3288 specific extensions to the Analogix Display Port
Required properties:
- compatible: "rockchip,rk3288-dp",
+ "rockchip,rk3368-dp",
"rockchip,rk3399-edp";
- reg: physical base address of the controller and length
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 080f05352195..acfcffc279ea 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -54,7 +54,7 @@
* @chip_type: specific chip type
*/
struct rockchip_dp_chip_data {
- u32 lcdsel_grf_reg;
+ int lcdsel_grf_reg;
u32 lcdsel_big;
u32 lcdsel_lit;
u32 chip_type;
@@ -207,9 +207,12 @@ static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder)
return;
}
- ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
- if (ret != 0)
- DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret);
+ if (dp->data->lcdsel_grf_reg >= 0) {
+ ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
+ if (ret != 0)
+ DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n",
+ ret);
+ }
clk_disable_unprepare(dp->grfclk);
}
@@ -455,8 +458,14 @@ static const struct rockchip_dp_chip_data rk3288_dp = {
.chip_type = RK3288_DP,
};
+static const struct rockchip_dp_chip_data rk3368_dp = {
+ .lcdsel_grf_reg = -1,
+ .chip_type = RK3288_DP,
+};
+
static const struct of_device_id rockchip_dp_dt_ids[] = {
{.compatible = "rockchip,rk3288-dp", .data = &rk3288_dp },
+ {.compatible = "rockchip,rk3368-dp", .data = &rk3368_dp },
{.compatible = "rockchip,rk3399-edp", .data = &rk3399_edp },
{}
};
--
2.19.2
