Add compatible strings for the SiFive U54 family of CPU cores to the RISC-V CPU compatible string documentation. The U54 CPU cores are described in: https://static.dev.sifive.com/FU540-C000-v1.0.pdf Cc: Rob Herring <robh+dt@xxxxxxxxxx> Cc: Mark Rutland <mark.rutland@xxxxxxx> Cc: Palmer Dabbelt <palmer@xxxxxxxxxx> Cc: Albert Ou <aou@xxxxxxxxxxxxxxxxx> Cc: devicetree@xxxxxxxxxxxxxxx Cc: linux-riscv@xxxxxxxxxxxxxxxxxxx Cc: linux-kernel@xxxxxxxxxxxxxxx Signed-off-by: Paul Walmsley <paul.walmsley@xxxxxxxxxx> Signed-off-by: Paul Walmsley <paul@xxxxxxxxx> --- Documentation/devicetree/bindings/riscv/cpus.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt b/Documentation/devicetree/bindings/riscv/cpus.txt index fb9d4f86f41f..d8d99b6b5386 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.txt +++ b/Documentation/devicetree/bindings/riscv/cpus.txt @@ -70,7 +70,8 @@ described below. Value type: <stringlist> Definition: must contain "riscv", may contain one or more of "sifive,rocket0", "sifive,e51", - "sifive,e5" + "sifive,e5", "sifive,u54-mc", "sifive,u54", + "sifive,u5" - mmu-type: Usage: optional Value type: <string> -- 2.20.0
