Quoting Anson Huang (2018-12-07 02:03:34) > i.MX7ULP has a Cortex-A7 CPU which can run in RUN mode > or HSRUN mode, it is controlled in SMC1 module. The RUN > mode and HSRUN mode will use different clock source for > ARM, "divcore" for RUN mode and "hsrun_divcore" for HSRUN > mode, so the control bits in SMC1 module can be abstracted > as a HW clock mux, this patch adds HSRUN mode related > clocks in SCG1 module and adds "arm" clock in SMC1 module > to support RUN mode and HSRUN mode switch. > > Latest clock tree in RUN mode as below: > > firc 0 0 0 48000000 0 0 50000 > firc_bus_clk 0 0 0 48000000 0 0 50000 > hsrun_scs_sel 0 0 0 48000000 0 0 50000 > hsrun_divcore 0 0 0 48000000 0 0 50000 > > sosc 3 3 3 24000000 0 0 50000 > spll_pre_sel 1 1 1 24000000 0 0 50000 > spll_pre_div 1 1 2 24000000 0 0 50000 > spll 1 1 2 528000000 0 0 50000 > spll_pfd0 1 1 1 500210526 0 0 50000 > spll_pfd_sel 1 1 0 500210526 0 0 50000 > spll_sel 1 1 0 500210526 0 0 50000 > scs_sel 1 1 0 500210526 0 0 50000 > divcore 1 1 0 500210526 0 0 50000 > arm 1 1 0 500210526 0 0 50000 > > Signed-off-by: Anson Huang <Anson.Huang@xxxxxxx> > --- Applied to clk-next
