There are HSRUN mode clock mux and divider in SCG1 module, and SMC1 can control i.MX7ULP CPU to run in RUN mode or HSRUN mode, the mode switch bits are actually a clock mux, add these clocks for clock driver and dtb to use. Signed-off-by: Anson Huang <Anson.Huang@xxxxxxx> --- include/dt-bindings/clock/imx7ulp-clock.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h index 008c5ee..21d872e 100644 --- a/include/dt-bindings/clock/imx7ulp-clock.h +++ b/include/dt-bindings/clock/imx7ulp-clock.h @@ -54,8 +54,10 @@ #define IMX7ULP_CLK_SOSC_BUS_CLK 41 #define IMX7ULP_CLK_FIRC_BUS_CLK 42 #define IMX7ULP_CLK_SPLL_BUS_CLK 43 +#define IMX7ULP_CLK_HSRUN_SYS_SEL 44 +#define IMX7ULP_CLK_HSRUN_CORE_DIV 45 -#define IMX7ULP_CLK_SCG1_END 44 +#define IMX7ULP_CLK_SCG1_END 46 /* PCC2 */ #define IMX7ULP_CLK_DMA1 0 @@ -106,4 +108,9 @@ #define IMX7ULP_CLK_PCC3_END 16 +/* SMC1 */ +#define IMX7ULP_CLK_ARM 0 + +#define IMX7ULP_CLK_SMC1_END 1 + #endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */ -- 2.7.4
