Add DT bindings documentation for the ARM display processor D71 and later
IPs.
Signed-off-by: James (Qian) Wang <james.qian.wang@xxxxxxx>
---
.../bindings/display/arm/arm,komeda.txt | 87 +++++++++++++++++++
1 file changed, 87 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/arm/arm,komeda.txt
diff --git a/Documentation/devicetree/bindings/display/arm/arm,komeda.txt b/Documentation/devicetree/bindings/display/arm/arm,komeda.txt
new file mode 100644
index 000000000000..d4b53c11b2a2
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/arm/arm,komeda.txt
@@ -0,0 +1,87 @@
+Device Tree bindings for ARM Komeda display driver
+
+Required properties:
+- compatible: Should be "arm,mali-d71"
+- reg: Physical base address and length of the registers in the system
+- interrupts: the interrupt line numbers of the device in the system
+- interrupt-names: contains the names of the IRQs in the order they were
+ provided in the "interrupts" property. Must contain: "DPU".
+- clocks: A list of phandle + clock-specifier pairs, one for each entry
+ in 'clock-names'
+- clock-names: A list of clock names. It should contain:
+ - "pclk": for the APB interface clock
+ - "mclk": for the main processor clock
+- #address-cells: Must be 1
+- #size-cells: Must be 0
+
+Required properties for sub-node: pipeline@nq
+Each device contains one or two pipeline sub-nodes (at least one), each
+pipeline node should provide properties:
+- reg: Zero-indexed identifier for the pipeline
+- clocks: A list of phandle + clock-specifier pairs, one for each entry
+ in 'clock-names'
+- clock-names: should contain:
+ - "aclk": AXI interface clock
+ - "pxclk": pixel clock
+
+- port: each pipeline connect to an encoder input port. The connection is
+ modelled using the OF graph bindings specified in
+ Documentation/devicetree/bindings/graph.txt
+
+Optional properties:
+ - memory-region: phandle to a node describing memory (see
+ Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
+ to be used for the framebuffer; if not present, the framebuffer may
+ be located anywhere in memory.
+
+Example:
+/ {
+...
+
+dp0: display@c00000 {
+#address-cells = <1>;
+#size-cells = <0>;
+compatible = "arm,mali-d71";
+reg = <0xc00000 0x20000>;
+interrupts = <0 168 4>;
+interrupt-names = "DPU";
+clocks = <&dpu_mclk>, <&dpu_aclk>;
+clock-names = "mclk", "pclk";
+
+pl0: pipeline@0 {
+clocks = <&fpgaosc2>, <&dpu_aclk>;
+clock-names = "pxclk", "aclk";
+reg = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dp0_pl0_out: endpoint {
+remote-endpoint = <&db_dvi0_in>;
+};
+};
+};
+};
+pl1: pipeline@1 {
+clocks = <&fpgaosc2>, <&dpu_aclk>;
+clock-names = "pxclk", "aclk";
+reg = <1>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dp0_pl1_out: endpoint {
+remote-endpoint = <&db_dvi1_in>;
+};
+};
+};
+};
+};
+...
+};
--
2.17.1
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